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19-3005; Rev 3; 7/07
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs
General Description
The MAX5290-MAX5295 dual, 12-/10-/8-bit, voltageoutput digital-to-analog converters (DACs) offer buffered outputs and a 3s maximum settling time at the 12-bit level. The DACs operate from a 2.7V to 5.25V analog supply and a separate 1.8V to 3.6V digital supply. The 20MHz 3-wire serial interface is compatible with SPITM, QSPITM, MICROWIRETM, and digital signal processor (DSP) protocol applications. Multiple devices can share a common serial interface in direct access or daisy-chained configuration. The MAX5290-MAX5295 provide two multifunctional, user-programmable, digital I/O ports. The externally selectable power-up states of the DAC outputs are either zero scale, midscale, or full scale. Software-selectable FAST and SLOW settling modes decrease settling time in FAST mode, or reduce supply current in SLOW mode. The MAX5290/MAX5291 are 12-bit DACs, the MAX5292/ MAX5293 are 10-bit DACs, and the MAX5294/MAX5295 are 8-bit DACs. The MAX5290/ MAX5292/MAX5294 provide unity-gain-configured output buffers, while the MAX5291/MAX5293/MAX5295 provide force-sense-configured output buffers. The MAX5290- MAX5295 are specified over the extended -40C to +85C temperature range, and are available in space-saving 4mm x 4mm, 16-pin thin QFN and 6.5mm x 5mm, 14-pin and 16-pin TSSOP packages.
Features
Dual, 12-/10-/8-Bit Serial DACs in 4mm x 4mm Thin QFN and TSSOP Packages 3s (max) 12-Bit Settling Time to 1/2 LSB Integral Nonlinearity 1 LSB (max) MAX5290/MAX5291 A-Grade (12-Bit) 1 LSB (max) MAX5292/MAX5293 (10-Bit) 1/2 LSB (max) MAX5294/MAX5295 (8-Bit) Guaranteed Monotonic, 1 LSB (max) DNL Two User-Programmable Digital I/O Ports Single +2.7V to +5.25V Analog Supply +1.8V to AVDD Digital Supply 20MHz 3-Wire SPI-/QSPI-/MICROWIRE- and DSP-Compatible Serial Interface Glitch-Free Outputs Power Up to Zero Scale, Midscale or Full Scale Unity-Gain- or Force-Sense-Configured Output Buffers
MAX5290-MAX5295
Ordering Information
PART MAX5290AEUD MAX5290BEUD MAX5290AETE* MAX5290BETE* MAX5291AEUE MAX5291BEUE MAX5291AETE* MAX5291BETE* MAX5292EUD MAX5292ETE* MAX5293EUE MAX5293ETE* MAX5294EUD MAX5294ETE* MAX5295EUE MAX5295ETE* TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 14 TSSOP 14 TSSOP 16 Thin QFN-EP** 16 Thin QFN-EP** 16 TSSOP 16 TSSOP 16 Thin QFN-EP** 16 Thin QFN-EP** 14 TSSOP 16 Thin QFN-EP** 16 TSSOP 16 Thin QFN-EP** 14 TSSOP 16 Thin QFN-EP** 16 TSSOP 16 Thin QFN-EP**
Applications
Portable Instrumentation Automatic Test Equipment (ATE) Digital Offset and Gain Adjustment Automatic Tuning Programmable Voltage and Current Sources Programmable Attenuators Industrial Process Controls Motion Control Microprocessor (P)-Controlled Systems Power Amplifier Control Fast Parallel-DAC to Serial-DAC Upgrades
Selector Guide and Pin Configurations appear at end of data sheet. SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
*Future product--contact factory for availability. Specifications are preliminary. **EP = Exposed paddle. 1
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs MAX5290-MAX5295
ABSOLUTE MAXIMUM RATINGS
AVDD to DVDD ........................................................................6V AGND to DGND ..................................................................0.3V AVDD to AGND, DGND.............................................-0.3V to +6V DVDD to AGND, DGND ............................................-0.3V to +6V FB_, OUT_, REF to AGND ........-0.3V to the lower of (AVDD + 0.3V) or +6V SCLK, DIN, CS, PU, DSP to DGND .......-0.3V to the lower of (DVDD + 0.3V) or +6V UPIO1, UPIO2 to DGND ...............-0.3V to the lower of (DVDD + 0.3V) or +6V Maximum Current into Any Pin .........................................50mA Continuous Power Dissipation (TA = +70C) 14-Pin TSSOP (derate 9.1mW/C above +70C) .........727mW 16-Pin TSSOP (derate 9.4mW/C above +70C) .........755mW 16-Pin Thin QFN (derate 16.9mW/C above +70C) .1349mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, AGND = 0, DGND = 0, VREF = 2.5V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER STATIC ACCURACY MAX5290/MAX5291 Resolution N MAX5292/MAX5293 MAX5294/MAX5295 VREF = 2.5V at AVDD = 2.7V, VREF = 4.096V at AVDD = 5.25V (Note 2) MAX5290A/MAX5291A (12-bit) MAX5290B/MAX5291B (12-bit) MAX5292/MAX5293 (10-bit) MAX5294/MAX5295 (8-bit) 2 0.5 0.125 12 10 8 1 4 LSB 1 0.5 1 5 5 5 5 5 MAX5290A/MAX5291A (12-bit) Gain Error GE Full-scale output MAX5290B/MAX5291B (12-bit) MAX5292/MAX5293 (10-bit) MAX5294/MAX5295 (8-bit) Gain-Error Drift 10 3 0.5 1 4 20 5 2 ppm of FS/C LSB 25 25 25 ppm of FS/C mV LSB Bits SYMBOL CONDITIONS MIN TYP MAX UNITS
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
Guaranteed monotonic (Note 2) MAX5290A/MAX5291A (12-bit), decimal code = 40 MAX5290B/MAX5291B (12-bit), decimal code = 82 MAX5292/MAX5293 (10-bit), decimal code = 21 MAX5294/MAX5295 (8-bit), decimal code = 5
Offset Error
VOS
Offset-Error Drift
2
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Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, AGND = 0, DGND = 0, VREF = 2.5V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Power-Supply Rejection Ratio REFERENCE INPUT Reference Input Range Reference Input Resistance Reference Leakage Current VREF RREF IREF Normal operation (no code dependence) Shutdown mode 0.25 145 200 0.5 1 AVDD V k A SYMBOL PSRR CONDITIONS Full-scale output, AVDD = 2.7V to 3.6V MIN TYP 200 MAX UNITS V/V
MAX5290-MAX5295
DAC OUTPUT CHARACTERISTICS SLOW mode, full scale Output Voltage Noise FAST mode, full scale Output Voltage Range (Note 4) DC Output Impedance Short-Circuit Current Power-Up Time Wake-Up Time Output OUT_ and FB_ Open-Circuit Leakage Current DIGITAL OUTPUTS (UPIO_) Output High Voltage Output Low Voltage VOH VOL ISOURCE = 2mA ISINK = 2mA DVDD 2.7V Input High Voltage VIH DVDD < 2.7V DVDD > 3.6V Input Low Voltage Input Leakage Current Input Capacitance VIL IIN CIN 2.7V DVDD 3.6V DVDD < 2.7V 0.1 10 2.4 0.7 x DVDD 0.8 0.6 0.2 1 A pF V V DVDD 0.5 0.4 V V AVDD = 3V, OUT_ to AGND, full scale, FAST mode From DVDD applied, interface is functional Coming out of shutdown, outputs settled Programmed in shutdown mode, force-sense outputs only Unity-gain output Force-sense output Unity gain Force sense Unity gain Force sense 0 0 38 45 30 40 0.01 60 85 67 140 110 AVDD AVDD / 2 V mA s s A VRMS
DIGITAL INPUTS (SCLK, CS, DIN, DSP, UPIO_)
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3
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs MAX5290-MAX5295
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, AGND = 0, DGND = 0, VREF = 2.5V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER PU INPUT Input High Voltage Input Low Voltage Input Leakage Current DYNAMIC PERFORMANCE Voltage-Output Slew Rate SR Fast mode Slow mode MAX5290/MAX5291 from code 322 to code 4095 to 1/2 LSB FAST mode MAX5292/MAX5293 from code 82 to code 1023 to 1/2 LSB MAX5294/MAX5295 from code 21 to code 255 to 1/2 LSB MAX5290/MAX5291 from code 322 to code 4095 to 1/2 LSB SLOW mode MAX5292/MAX5293 from code 82 to code 1023 to 1/2 LSB MAX5294/MAX5295 from code 21 to code 255 to 1/2 LSB FB_ Input Voltage FB_ Input Current Reference -3dB Bandwidth (Note 6) Digital Feedthrough Digital-to-Analog Glitch Impulse DAC-to-DAC Crosstalk Unity gain Force sense CS = DVDD, code = zero scale, any digital input from 0 to DVDD and DVDD to 0, f = 100kHz Major carry transition (Note 3) 200 150 0.1 2 15 0 3.6 1.6 2 1.5 1 3 2.5 2 3 3 2 s 6 6 4 VREF / 2 0.1 V A kHz nV-s nV-s nV-s V/s VIH-PU VIL-PU IIN-PU PU still considered floating when connected to a tri-state bus DVDD 200mV 200 200 V mV nA SYMBOL CONDITIONS MIN TYP MAX UNITS
Voltage-Output Settling Time (Note 5)
4
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Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, AGND = 0, DGND = 0, VREF = 2.5V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER POWER REQUIREMENTS Analog Supply Voltage Range Digital Supply Voltage Range AVDD DVDD SLOW mode, all digital inputs Unity gain at DGND or DVDD, no load, VREF = 2.5V Force sense Operating Supply Current IAVDD + IDVDD FAST mode, all digital inputs at DGND or DVDD, no load, VREF = 2.5V Unity gain Force sense 2.70 1.8 0.55 0.9 0.85 1.2 5.25 AVDD 0.8 1.2 2 mA 2 V V mA mA SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5290-MAX5295
Shutdown Supply Current
IAVDD(SHDN) No clocks, all digital inputs at DGND or DVDD, all + DACs in shutdown mode IDVDD(SHDN)
0.5
1.0
A
TIMING CHARACTERISTICS--DSP Mode Disabled (3V, 3.3V Logic) (Figure 1)
(DVDD = 2.7V to 5.25V, DGND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SCLK Frequency SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time SCLK Rise to CS Fall Setup Time DIN to SCLK Rise Setup Time DIN to SCLK Rise Hold Time SCLK Rise to DOUTDC1 Valid Propagation Delay SCLK Fall to DOUT_ Valid Propagation Delay CS Rise to SCLK Rise Hold Time CS Pulse-Width High SYMBOL fSCLK tCH tCL tCSS tCSH tCS0 tDS tDH tDO1 tDO2 tCS1 tCSW CL = 20pF, UPIO_ = DOUTDC1 mode CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB mode MICROWIRE and SPI modes 0 and 3 10 45 (Note 7) (Note 7) CONDITIONS 2.7V < DVDD < 5.25V 20 20 10 5 10 12 5 30 30 MIN TYP MAX 20 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns
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5
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs MAX5290-MAX5295
TIMING CHARACTERISTICS--DSP Mode Disabled (3V, 3.3V Logic) (Figure 1) (continued)
(DVDD = 2.7V to 5.25V, DGND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER UPIO TIMING CHARACTERISTICS DOUT Tri-State Time when Exiting DOUTDC0, DOUTDC1, or DOUTRB UPIO Modes DOUTRB Tri-State Time from CS Rise DOUTRB Tri-State Enable Time from 8th SCLK Rise LDAC Pulse-Width Low LDAC Effective Delay CLR, MID, SET Pulse-Width Low GPO Output Settling Time GPO Output High-Impedance Time tDOZ CL = 20pF, from end of write cycle to UPIO_ in high impedance CL = 20pF, from rising edge of CS to UPIO_ in high impedance CL = 20pF, from 8th rising edge of SCLK to UPIO_ driven out of tri-state Figure 5 Figure 6 Figure 5 Figure 6 0 20 100 20 100 100 100 ns SYMBOL CONDITIONS MIN TYP MAX UNITS
tDRBZ tZEN tLDL tLDS tCMS tGP tGPZ
20
ns ns ns ns ns ns ns
TIMING CHARACTERISTICS--DSP Mode Disabled (1.8V Logic) (Figure 1)
(DVDD = 1.8V to 5.25V, DGND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SCLK Frequency SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time SCLK Rise to CS Fall Setup Time DIN to SCLK Rise Setup Time DIN to SCLK Rise Hold Time SCLK Rise to DOUTDC1 Valid Propagation Delay SCLK Fall to DOUT_ Valid Propagation Delay CS Rise to SCLK Rise Hold Time CS Pulse-Width High SYMBOL fSCLK tCH tCL tCSS tCSH tCS0 tDS tDH tDO1 tDO2 tCS1 tCSW CL = 20pF, UPIO_ = DOUTDC1 mode CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB mode MICROWIRE and SPI modes 0 and 3 20 90 (Note 7) (Note 7) CONDITIONS 1.8V < DVDD < 5.25V 40 40 20 0 10 20 5 60 60 MIN TYP MAX 10 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns
6
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Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs
TIMING CHARACTERISTICS--DSP Mode Disabled (1.8V Logic) (Figure 1) (continued)
(DVDD = 1.8V to 5.25V, DGND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5290-MAX5295
UPIO_ TIMING CHARACTERISTICS DOUT Tri-State Time when Exiting DOUTDC0, DOUTDC1, or DOUTRB UPIO Modes DOUTRB Tri-State Time from CS Rise DOUTRB Tri-State Enable Time from 8th SCLK Rise LDAC Pulse-Width Low LDAC Effective Delay CLR, MID, SET Pulse-Width Low GPO Output Settling Time GPO Output High-Impedance Time tDOZ CL = 20pF, from end of write cycle to UPIO_ in high impedance CL = 20pF, from rising edge of CS to UPIO_ in high impedance CL = 20pF, from 8th rising edge of SCLK to UPIO_ driven out of tri-state Figure 5 Figure 6 Figure 5 Figure 6 0 40 200 40 200 200 200 ns
tDRBZ tZEN tLDL tLDS tCMS tGP tGPZ
40
ns ns ns ns ns ns ns
TIMING CHARACTERISTICS--DSP Mode Enabled (3V, 3.3V Logic) (Figure 2)
(DVDD = 2.7V to 5.25V, DGND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SCLK Frequency SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall to SCLK Fall Setup Time DSP Fall to SCLK Fall Setup Time SCLK Fall to CS Rise Hold Time SCLK Fall to CS Fall Delay SCLK Fall to DSP Fall Delay DIN to SCLK Fall Setup Time DIN to SCLK Fall Hold Time SCLK Rise to DOUT_ Valid Propagation Delay SCLK Fall to DOUTDC0 Valid Propagation Delay CS Rise to SCLK Fall Hold Time CS Pulse-Width High DSP Pulse-Width High DSP Pulse-Width Low SYMBOL fSCLK tCH tCL tCSS tDSS tCSH tCS0 tDS0 tDS tDH tDO1 tDO2 tCS1 tCSW tDSW tDSPWL (Note 8) CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB mode CL = 20pF, UPIO_ = DOUTDC0 mode MICROWIRE and SPI modes 0 and 3 10 45 20 20 (Note 7) (Note 7) CONDITIONS 2.7V < DVDD < 5.25V 20 20 10 10 5 10 10 12 5 30 30 MIN TYP MAX 20 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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7
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs MAX5290-MAX5295
TIMING CHARACTERISTICS--DSP Mode Enabled (3V, 3.3V Logic) (Figure 2) (continued)
(DVDD = 2.7V to 5.25V, DGND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS UPIO_ TIMING CHARACTERISTICS DOUT Tri-State Time when Exiting DOUTDC0, DOUTDC1, or DOUTRB UPIO Modes DOUTRB Tri-State Time from CS Rise DOUTRB Tri-State Enable Time from 8th SCLK Fall LDAC Pulse-Width Low LDAC Effective Delay CLR, MID, SET Pulse-Width Low GPO Output Settling Time GPO Output High-Impedance Time tDOZ CL = 20pF, from end of write cycle to UPIO_ in high impedance CL = 20pF, from rising edge of CS to UPIO_ in high impedance CL = 20pF, from 8th falling edge of SCLK to UPIO_ driven out of tri-state Figure 5 Figure 6 Figure 5 Figure 6 0 20 100 20 100 100 100 ns
tDRBZ tZEN tLDL tLDS tCMS tGP tGPZ
20
ns ns ns ns ns ns ns
TIMING CHARACTERISTICS--DSP Mode Enabled (1.8V Logic) (Figure 2)
(DVDD = 1.8V to 5.25V, DGND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SCLK Frequency SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall to SCLK Fall Setup Time DSP Fall to SCLK Fall Setup Time SCLK Fall to CS Rise Hold Time SCLK Fall to CS Fall Delay SCLK Fall to DSP Fall Delay DIN to SCLK Fall Setup Time DIN to SCLK Fall Hold Time SCLK Rise to DOUT_ Valid Propagation Delay SCLK Fall to DOUTDC0 Valid Propagation Delay CS Rise to SCLK Fall Hold Time CS Pulse-Width High DSP Pulse-Width High DSP Pulse-Width Low SYMBOL fSCLK tCH tCL tCSS tDSS tCSH tCS0 tDS0 tDS tDH tDO1 tDO2 tCS1 tCSW tDSW tDSPWL (Note 8) CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB mode CL = 20pF, UPIO_ = DOUTDC0 mode MICROWIRE and SPI modes 0 and 3 20 90 40 40 (Note 7) (Note 7) CONDITIONS 1.8V < DVDD < 5.25V 40 40 20 20 0 10 15 20 5 60 60 MIN TYP MAX 10 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
8
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Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs
TIMING CHARACTERISTICS--DSP Mode Enabled (1.8V Logic) (Figure 2) (continued)
(DVDD = 1.8V to 5.25V, DGND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS UPIO_ TIMING CHARACTERISTICS DOUT Tri-State Time when Exiting DOUTDC0, DOUTDC1, or DOUTRB UPIO_ Modes DOUTRB Tri-State Time from CS Rise DOUTRB Tri-State Enable Time from 8th SCLK Fall LDAC Pulse-Width Low LDAC Effective Delay CLR, MID, SET Pulse-Width Low GPO Output Settling Time GPO Output High-Impedance Time tDOZ CL = 20pF, from end of write cycle to UPIO_ in high impedance CL = 20pF, from rising edge of CS to UPIO_ in high impedance CL = 20pF, from 8th falling edge of SCLK to UPIO_ driven out of tri-state Figure 5 Figure 6 Figure 5 Figure 6 0 40 200 40 200 200 200 ns
MAX5290-MAX5295
tDRBZ tZEN tLDL tLDS tCMS tGP tGPZ
40
ns ns ns ns ns ns ns
Note 1: For the force-sense versions, FB_ is connected to its respective OUT_. VOUT(max) = VREF / 2, unless otherwise noted. Note 2: Linearity guaranteed from decimal code 40 to 4095 for the MAX5290A/MAX5291A (12-bit, A-grade), code 82 to 4095 for the MAX5290B/MAX5291B (12-bit, B-grade), code 21 to 1023 for the MAX5292/MAX5293 (10-bit), and code 5 to 255 for the MAX5294/MAX5295 (8-bit). Note 3: DAC-to-DAC crosstalk is measured as follows: outputs of DACA and DACB are set to full scale and the output of DACB is measured. While keeping DACB unchanged, the output of DACA is transitioned to zero scale and the VOUT of DACB is measured. The procedure is repeated with DACA and DACB interchanged. DAC-to-DAC crosstalk is the maximum VOUT measured. Note 4: Represents the functional range. The linearity is guaranteed at VREF = 2.5V. See the Typical Operating Characteristics section for linearity at other voltages. Note 5: Guaranteed by design. Note 6: The reference -3dB bandwidth is measured with a 0.1VP-P sine wave on VREF and with the input code at full scale. Note 7: In some daisy-chain modes, data is required to be clocked in on one clock edge and the shifted data clocked out on the following edge. In the case of a 1/2 clock-period delay, it is necessary to increase the minimum high/low clock times to 25ns (2.7V) or 50ns (1.8V). Note 8: The falling edge of DSP starts a DSP-type bus cycle, provided that CS is also active low to select the device. DSP active low and CS active low must overlap by a minimum of 10ns (2.7V) or 20ns (1.8V). CS can be permanently low in this mode of
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Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs MAX5290-MAX5295
Typical Operating Characteristics
(AVDD = DVDD = 3V, VREF = 2.5V, RL = 10k, CL = 100pF, speed mode = FAST, PU = floating, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (MAX5290A)
MAX5290 toc01
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (MAX5291A)
MAX5290 toc02
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (12-BIT)
3 2 INL (LSB) 1 0 -1 -2 -3 -4 UNITY GAIN B-GRADE
MAX5290 toc03
0.4 0.2 0 INL (LSB)
0.15 0.10 0.05 0 INL (LSB) -0.05 -0.10 -0.15 -0.20 -0.25 -0.30
4
-0.2 -0.4 -0.6 -0.8 0 1000 2000 3000 4000 4096 INPUT CODE
-0.35 0 1000 2000 3000 4000 4096 INPUT CODE
0
1024
2048
3072
4096
DIGITAL INPUT CODE
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (10-BIT)
MAX5290 toc04
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (8-BIT)
MAX5290 toc05
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (12-BIT)
UNITY GAIN
MAX5290 toc06
1.00 0.75 0.50 INL (LSB)
UNITY GAIN
0.50 UNITY GAIN
0.2
0.25 DNL (LSB) 0 256 INL (LSB)
0.1
0.25 0 -0.25 -0.50 -0.75 -1.00 0 256 512 768 1024 DIGITAL INPUT CODE
0
0
-0.25
-0.1
-0.50 64 128 192 DIGITAL INPUT CODE
-0.2 0 1024 2048 3072 4096 DIGITAL INPUT CODE
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (10-BIT)
MAX5290 toc07
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (8-BIT)
MAX5290 toc08
INTEGRAL NONLINEARITY vs. TEMPERATURE (A-GRADE)
0.35 0.30 INL (LSB) 0.25 0.20 0.15 FORCE SENSE UNITY GAIN
MAX5290 toc09
0.050 UNITY GAIN
0.02 UNITY GAIN
0.40
0.025 DNL (LSB) DNL (LSB)
0.01
0
0
-0.025
-0.01
0.10 0.05 MIDSCALE
-0.050 0 256 512 768 1024 DIGITAL INPUT CODE
-0.02 0 64 128 192 256 DIGITAL INPUT CODE
0 -40 -15 10 35 60 85 TEMPERATURE (C)
10
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Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs MAX5290-MAX5295
Typical Operating Characteristics (continued)
(AVDD = DVDD = 3V, VREF = 2.5V, RL = 10k, CL = 100pF, speed mode = FAST, PU = floating, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. TEMPERATURE (12-BIT)
MAX5290 toc10
DIFFERENTIAL NONLINEARITY vs. TEMPERATURE (12-BIT)
UNITY GAIN
MAX5290 toc11
INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE (MAX5290A)
0.45 0.40 0.35 INL (LSB) 0.30 0.25 0.20 0.15
MAX5290 toc12
4
UNITY GAIN B-GRADE
0.2
0.50
2 DNL (LSB) INL (LSB)
0.1
0
0
-2
-0.1
0.10 0.05
-4 -40 -15 10 35 60 85 TEMPERATURE (C)
-0.2 -40 -15 10 35 60 85 TEMPERATURE (C)
0 1.0 1.5 2.0 2.5 3.0 VREF (V) 3.5 4.0 4.5 5.0
INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE (MAX5291A)
MAX5290 toc13
OFFSET ERROR vs. TEMPERATURE (A-GRADE)
0.7 OFFSET ERROR (mV) 0.6 0.5 0.4 0.3 0.2 0.1 0 -10 -40 -15 10 35 60 85 -40 FORCE SENSE CODE = 40 UNITY GAIN UNITY GAIN: 1 LSB = 0.6mV FORCE SENSE: 1 LSB = 0.3mV
MAX5290 toc14
OFFSET ERROR vs. TEMPERATURE
MAX5290 toc15
1.0 0.9 0.8 0.7 INL (LSB) 0.6 0.5 0.4 0.3 0.2 0.1 0 1.0 1.5 2.0 2.5 3.0 VREF (V) 3.5 4.0 4.5
0.8
0
-2 OFFSET ERROR (LSB)
FORCE SENSE UNITY GAIN
-4
-6
-8 UNITY GAIN: 1 LSB = 0.6mV FORCE SENSE: 1 LSB = 0.3mV -15 10 35 60 85
5.0
TEMPERATURE (C)
TEMPERATURE (C)
GAIN ERROR vs. TEMPERATURE (A-GRADE)
MAX5290 toc16
GAIN ERROR vs. TEMPERATURE
MAX5290 toc17
REFERENCE INPUT BANDWIDTH
VREF = 0.1VP-P AT 2.5VDC 0 -5 GAIN (dB)
MAX5290 toc18
0.15 0.10 0.05 GAIN ERROR (LSB) 0 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 -40 -15 10 35 60 FORCE SENSE UNITY GAIN UNITY GAIN: 1 LSB = 0.6mV FORCE SENSE: 1 LSB = 0.3mV
0 UNITY GAIN: 1 LSB = 0.6mV FORCE SENSE: 1 LSB = 0.3mV -2 GAIN ERROR (LSB)
5
-4
FORCE SENSE
-10 -15 -20
-6 UNITY GAIN -8
-25 -10 85 -40 -15 10 35 60 85 -30 0 1k 10k 100k 1M 10M TEMPERATURE (C) FREQUENCY (Hz)
TEMPERATURE (C)
______________________________________________________________________________________
11
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs MAX5290-MAX5295
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. DIGITAL INPUT CODE (FORCE SENSE)
MAX5290 toc19
SUPPLY CURRENT vs. DIGITAL INPUT CODE (UNITY GAIN)
MAX5290 toc20
SUPPLY CURRENT vs. SUPPLY VOLTAGE (FORCE SENSE)
1.3 1.2 SUPPLY CURRENT (mA) 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 SLOW MODE I = IAVDD + IDVDD AVDD = DVDD NO LOAD FAST MODE
MAX5290 toc21
1.2 1.1 1.0 SUPPLY CURRENT (mA) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 SLOW MODE 12-BIT NO LOAD 1024 2048 3072
0.8 0.7 SUPPLY CURRENT (mA) 0.6 0.5 0.4 0.3 0.2 0.1 0 0 SLOW MODE 12-BIT NO LOAD 1024 2048 3072
1.4
4096
4096
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
DIGITAL INPUT CODE
DIGITAL INPUT CODE
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. SUPPLY VOLTAGE (UNITY GAIN)
MAX5290 toc22
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5290 toc23
OFFSET ERROR vs. TEMPERATURE
4 3 OFFSET ERROR (LSB) 2 1 0 -1 -2 -3 -4 -5 FORCE SENSE UNITY GAIN B-GRADE UNITY GAIN: 1 LSB = 1mV FORCE SENSE: 1 LSB = 0.5mV
MAX5290 toc24
1.0 0.9 0.8 SUPPLY CURRENT (mA) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 SLOW MODE I = IAVDD + IDVDD AVDD = DVDD NO LOAD FAST MODE
100 SHUTDOWN SUPPLY CURRENT (nA) 95 90 85 80 75 70 65 60 55 50 AVDD = DVDD I = IAVDD + IDVDD NO LOAD 2.7 3.1 3.5 3.9 4.3 4.7 5.1 UNITY GAIN FORCE SENSE
5
5.5
5.5
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
GAIN ERROR vs. TEMPERATURE
MAX5290 toc25
OUTPUT VOLTAGE vs. OUTPUT SOURCE/SINK CURRENT
2.15 OUTPUT VOLTAGE (V) 2.10 2.05 2.00 1.95 1.90 1.85 1.80 UNITY GAIN VREF = 4.096V -40 -30 -20 -10 0 10 20 30 40 MIDSCALE
MAX5290 toc26
MAJOR-CARRY TRANSITION GLITCH
MAX5290 toc27
5 4 3 GAIN ERROR (LSB) 2 1 0 -1 -2 -3 -4 -5 -40 -15 10 35 60 FORCE SENSE UNITY GAIN B-GRADE UNITY GAIN: 1 LSB = 1mV FORCE SENSE: 1 LSB = 0.5mV
2.20
OUT_ (AC-COUPLED) 10mV/div
CS 2V/div
85
200ns/div
TEMPERATURE (C)
IOUT (mA)
12
______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs MAX5290-MAX5295
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
SETTLING TIME POSITIVE
MAX5290 toc28
SETTLING TIME NEGATIVE
MAX5290 toc29
REFERENCE INPUT BANDWIDTH
MAX5290 toc30
5 0
FULL-SCALE TRANSITION
FULL-SCALE TRANSITION OUT_ 2V/div GAIN (dB) CS 2V/div CS 2V/div
OUT_ 2V/div
-5 -10 -15 -20 -25
VREF = 0.1VP-P AT 4.096VDC UNITY GAIN 1 10 100 FREQUENCY (kHz) 1000 10,000
400ns/div
400ns/div
REFERENCE FEEDTHROUGH AT 1kHz
-22 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -142 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FREQUENCY (kHz)
MAX5290 toc31
DAC-TO-DAC CROSSTALK
MAX5290 toc32
DIGITAL FEEDTHROUGH
MAX5290 toc33
OUTB 1mV/div
OUT_ (AC-COUPLED) 10mV/div
OUTA 2V/div
SCLK 2V/div
100s/div
1s/div
POWER-UP GLITCH
MAX5290 toc34
EXITING SHUTDOWN TO MIDSCALE
MAX5290 toc35
AVDD 2V/div
OUT_ 1V/div
OUT_ 1V/div PU = FLOATING 20s/div 10s/div PU = FLOATING
UPIO_ 2V/div
______________________________________________________________________________________
13
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs MAX5290-MAX5295
Pin Description
PIN MAX5290 MAX5292 MAX5294 THIN QFN 1 2 3 4 5 6 7 8 9 -- 10 -- 11, 13 12 TSSOP 2 3 4 5 6 7 8 9 10 -- 11 -- -- 12 MAX5291 MAX5293 MAX5295 THIN QFN 1 2 3 4 5 6 7 8 9 10 11 12 -- 13 TSSOP 3 4 5 6 7 8 9 10 11 12 13 14 -- 15 DSP DIN CS SCLK DVDD DGND AGND AVDD OUTB FBB REF FBA N.C. OUTA Clock Enable. Connect DSP to DVDD at power-up to transfer data on the rising edge of SCLK. Connect DSP to DGND at power-up to transfer data on the falling edge of SCLK. Serial Data Input Active-Low Chip-Select Input Serial Clock Input Digital Supply Digital Ground Analog Ground Analog Supply DACB Output Feedback for DACB Output Buffer Reference Input Feedback for DACA Output Buffer No Connection. Not internally connected. DACA Output Power-Up State Select Input. Connect PU to DVDD to set OUTA and OUTB to full scale upon power-up. Connect PU to DGND to set OUTA and OUTB to zero upon power-up. Leave PU floating to set OUTA and OUTB to midscale upon power-up. User-Programmable Input/Output 2 User-Programmable Input/Output 1 Exposed Paddle (QFN Only). Not internally connected. Do not connect to circuitry. NAME FUNCTION
14
13
14
16
PU
15 16 --
14 1 --
15 16 --
1 2 --
UPIO2 UPIO1 EP
14
______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs
Functional Diagrams
MAX5290-MAX5295
AVDD
DVDD
AGND
DGND
CS SCLK DIN
SERIAL INTERFACE CONTROL
MAX5290 MAX5292 MAX5294
DSP
16-BIT SHIFT REGISTER MUX DOUT REGISTER
UPIO1 UPIO2
UPIO1 AND UPIO2 LOGIC
POWER-DOWN LOGIC AND REGISTER
PU
DECODE CONTROL OUTA INPUT REGISTER DAC REGISTER DAC A
REF
OUTB INPUT REGISTER DAC REGISTER DAC B
______________________________________________________________________________________
15
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs MAX5290-MAX5295
Functional Diagrams (continued)
AVDD
DVDD
AGND
DGND
CS SCLK DIN
SERIAL INTERFACE CONTROL
MAX5291 MAX5293 MAX5295
DSP
16-BIT SHIFT REGISTER MUX DOUT REGISTER
UPIO1 UPIO2
UPIO1 AND UPIO2 LOGIC
POWER-DOWN LOGIC AND REGISTER FBA
PU
DECODE CONTROL
OUTA INPUT REGISTER DAC REGISTER DAC A
REF
FBB
OUTB INPUT REGISTER DAC REGISTER DAC B
16
______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs MAX5290-MAX5295
Detailed Description
The MAX5290-MAX5295 dual, 12-/10-/8-bit, voltageoutput digital-to-analog converters (DACs) offer buffered outputs and a 3s maximum settling time at the 12-bit level. The DACs operate from a single 2.7V to 5.25V analog supply and a separate 1.8V to AVDD digital supply. The MAX5290-MAX5295 include an input register and DAC register for each channel and a 16-bit data-in/data-out shift register. The 3-wire serial interface is compatible with SPI, QSPI, MICROWIRE, and DSP applications. The MAX5290-MAX5295 provide two user-programmable digital I/O ports, which are programmed through the serial interface. The externally selectable power-up states of the DAC outputs are either zero scale, midscale, or full scale. Use the serial interface to set the shutdown output impedance of the amplifiers to 1k or 100k for the MAX5290/MAX5292/MAX5294 and 1k or high impedance for the MAX5291/MAX5293/MAX5295. The DAC outputs can drive a 2k (typ) load and are stable with up to 500pF (typ) of capacitive load.
Power-On Reset
At power-up, all DAC outputs power up to full scale, midscale, or zero scale, depending on the configuration of the PU input. Connect PU to DVDD to set OUT_ to full scale upon power-up. Connect PU to DGND to set OUT_ to zero scale upon power-up. Leave PU floating to set OUT_ to midscale.
Digital Interface
The MAX5290-MAX5295 use a 3-wire serial interface that is compatible with SPI, QSPI, MICROWIRE, and DSPs (Figures 1 and 2). Connect DSP to DVDD before power-up to clock data in on the rising edge of SCLK. Connect DSP to DGND before power-up to clock data in on the falling edge of SCLK. After power-up, the device enters DSP frame sync mode on the first rising edge of DSP. Refer to the Programmer's Handbook for details. Each MAX5290-MAX5295 includes a 16-bit input shift register. The data is loaded into the input shift register through the serial interface. The 16 bits can be sent in two serial 8-bit packets or one 16-bit word (CS must remain low until all 16 bits are transferred). The data is loaded MSB first. For the MAX5290/MAX5291, the 16 bits consist of 4 control bits (C3-C0) and 12 data bits (D11-D0) (see Table 1). For the 10-bit MAX5292/ MAX5293 devices, D11-D2 are the data bits and D1 and D0 are sub-bits. For the 8-bit MAX5294/ MAX5295 devices, D11-D4 are the data bits and D3-D0 are sub-bits. Set all sub-bits to zero for optimum performance. Each DAC channel includes two registers: an input register and the DAC register. At power-up, the DAC output is set according to the state of PU. The DACs are double-buffered, which allows any of the following for each channel: * Loading the input register without updating the DAC register * Loading the DAC register without updating the input register * Updating the DAC register from the input register * Updating the input and DAC registers simultaneously
Reference Input
The reference input, REF, accepts both AC and DC values with a voltage range extending from 0.25V to AVDD. The voltage at REF (VREF) sets the full-scale output of the DACs. Determine the output voltage using the following equation: Unity-gain versions: VOUT_ = (VREF x CODE) / 2N Force-sense versions (FB_ connected to OUT_): VOUT = 0.5 x (VREF x CODE) / 2N where CODE is the numeric value of the DAC's binary input code and N is the bits of resolution. For the MAX5290/MAX5291, N = 12 and CODE ranges from 0 to 4095. For the MAX5292/MAX5293, N = 10 and CODE ranges from 0 to 1023. For the MAX5294/ MAX5295, N = 8 and CODE ranges from 0 to 255.
Output Buffers
The DACA and DACB output-buffer amplifiers of the MAX5290-MAX5295 are unity-gain stable with rail-torail output voltage swings and a typical slew rate of 5.7V/s. The MAX5290/MAX5292/MAX5294 provide unity-gain outputs, while the MAX5291/MAX5293/ MAX5295 provide force-sense outputs. For the MAX5291/MAX5293/MAX5295, access to the output amplifier's inverting input provides flexibility in output gain setting and signal conditioning (see the Applications Information section). The MAX5290-MAX5295 offer FAST and SLOW-settling time modes. In the FAST mode, the settling time is 3s (max), and the supply current is 2mA (max). In the SLOW mode, the settling time is 6s (max), and the supply current drops to 0.8mA (max). See the Digital Interface section for settling-time mode programming details.
______________________________________________________________________________________
17
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs MAX5290-MAX5295
Table 1. Serial Write Data Format
MSB CONTROL BITS C3 C2 C1 C0 D11 D10 D9 D8
tCH SCLK tCL tDS DIN tCS0 tCSS CS tCSW tDO1 DOUTDC1* tDO2 DOUTDC0 OR DOUTRB* DOUT VALID DOUT VALID tCS1 C3 tDH C2 C1 D0 tCSH
16 BITS OF SERIAL DATA DATA BITS D7 D6 D5 D4 D3 D2 D1
LSB D0
*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT). SEE THE DATA OUTPUT SECTION FOR DETAILS.
Figure 1. Serial-Interface Timing Diagram (DSP Mode Disabled)
tCL SCLK tDS DIN tCS0 C3 tDH tCSS CS tCSW tDS0 DSP tDSW DOUTDC0* tD01 DOUTDC1 OR DOUTRB* DOUT VALID tDSPWL tD02 DOUT VALID tDSS tCSH C2 tCH C1 D0
tCS1
*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT). SEE THE DATA OUTPUT SECTION FOR DETAILS.
Figure 2. Serial-Interface Timing Diagram (DSP Mode Enabled) 18 ______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs
Serial-Interface Programming Commands
Tables 2a, 2b, and 2c provide all of the serial-interface programming commands for the MAX5290-MAX5295. Table 2a shows the basic DAC programming commands, Table 2b gives the advanced-feature programming commands, and Table 2c provides the 24-bit read commands. Figures 3 and 4 illustrate the serialinterface diagrams for read and write operations.
MICROWIRE VDD SK SO I/O VDD
Loading Input and DAC Registers
The MAX5290-MAX5295 contain a 16-bit shift register that is followed by a 12-bit input register and a 12-bit DAC register for each channel (see the Functional Diagrams). Tables 3, 4, and 5 highlight a few of the commands for the loading of the input and DAC registers. See Table 2a for all DAC programming commands.
VDD
MAX5290-MAX5295
SPI OR QSPI DVDD DSP SCLK DIN CS
MAX5290- MAX5295
VDD SCK MOSI SS OR I/O
DVDD DSP SCLK DIN CS
MAX5290- MAX5295
MICROWIRE OR SPI (CPOL = 0, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE: CS SCLK CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
COMMAND TAKES EFFECT HERE ONLY IF SCLK COUNT = N 16
DIN
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SPI (CPOL = 1, CPHA = 1) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE: CS SCLK CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
COMMAND TAKES EFFECT HERE ONLY IF SCLK COUNT = N 16
DIN
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 3. MICROWIRE and SPI (CPOL = 0, CPHA = 0 or CPOL = 1, CPHA = 1) DAC Writes
DSP VSS TCLK, SCLK, OR CLKX DT OR DX TFS OR FSX SPI OR QSPI
MAX5290- DGND MAX5295
DSP SCLK DIN CS
MAX5290-
VSS SCK MOSI SS OR I/O DGND MAX5295 DSP SCLK DIN CS
DSP OR SPI (CPOL = 0, CPHA = 1) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE: CS SCLK CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
COMMAND TAKES EFFECT HERE ONLY IF SCLK COUNT = N 16
DIN
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DSP OR SPI (CPOL = 1, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE: CS SCLK CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
COMMAND TAKES EFFECT HERE ONLY IF SCLK COUNT = N 16
DIN
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 4. DSP and SPI (CPOL = 0, CPHA = 1 or CPOL = 1, CPHA = 0) DAC Writes ______________________________________________________________________________________ 19
MAX5290-MAX5295
DATA BITS D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D1 FUNCTION
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs
20
0 D11 D10 D9 D8 D7 D6 D5 D4 D3/0 D2/0 D1/0 D0/0 Load input register A from shift register; DAC registers are unchanged. DAC outputs are unchanged.* 1 D11 D10 D9 D8 D7 D6 D5 D4 D3/0 D2/0 D1/0 D0/0 Load DAC register A from shift register; input registers are unchanged. DAC outputs are updated.* Load input register A and DAC register A from shift register. DAC outputs are updated.* Load input register B; DAC registers are unchanged. DAC outputs are unchanged.* Load DAC register B from shift register; input registers are unchanged. DAC outputs are updated.* Load input register B and DAC register B from shift register. DAC outputs are updated.* Command is ignored. Command is ignored. X X X X D1/0 X X D0/0 Command is ignored. Command is ignored. Command is ignored. Command is ignored. Load all input registers from the shift register; all DAC registers are unchanged. All DAC outputs are unchanged.* D3/0 D2/0 D3/0 D2/0 D1/0 D0/0 Load all input and DAC registers from shift register. DAC outputs are updated.* D4 0 1 D11 D10 D9 D8 D7 D6 D5 D4 D3/0 D2/0 D1/0 D0/0 D11 D10 D9 D8 D7 D6 D5 D4 D3/0 D2/0 D1/0 D0/0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3/0 D2/0 D1/0 D0/0 1 0 1 0 1 0 1 0 D11 D10 D9 D8 D7 D6 D5 D4 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3/0 D2/0 D1/0 D0/0 1 D11 D10 D9 D8 D7 D6 D5
Table 2a. DAC Programming Commands
DATA
CONTROL BITS
C3
C2
C1
C0
LOADING INPUT AND DAC REGISTERS A AND B
DIN
0
0
0
DIN
0
0
0
DIN
0
0
1
DIN
0
0
1
DIN
0
1
0
DIN
0
1
0
DIN
0
1
1
DIN
0
1
1
DIN
1
0
0
DIN
1
0
0
DIN
1
0
1
DIN
1
0
1
DIN
1
1
0
______________________________________________________________________________________
DIN
1
1
0
X = Don't care.
*For the MAX5292/MAX5293 (10-bit version), D11-D2 are the significant bits and D1 and D0 are sub-bits. For the MAX5294/MAX5295 (8-bit version), D11-D4 are the significant bits and D3-D0 are sub-bits. Set all sub-bits to zero during the write commands.
Table 2b. Advanced-Feature Programming Commands
DATA BITS D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION C0 D1
DATA
CONTROL BITS
C3
C2
C1
SELECT BITS
DIN
1
1
1
0
0
0
X
X
X
X
X
X
X
X
MB
MA
Load DAC register A from input register A when MA is 1. DAC register A is unchanged if MA is 0. Load DAC register B from input register B when MB is 1. DAC register B is unchanged if MB is 0.
SHUTDOWN-MODE BITS 0 0 X X X X X X X X X PDB1 PDB0 PDA1 0 1 1 X X X X X X X X X PDA0 0 1 0 X X X X X PDB1 PDB0 PDA1 PDA0 Write DACA and DACB shutdown mode bits. See Table 8. Read DACA and DACB shutdown mode bits.
DIN
1
1
1
DIN
1
1
1
DOUTRB
X
X
X
UPIO CONFIGURATION BITS 0 0 X X X X X UP3-2 UP2-2 UP1-2 UP0-2 1 0 1 X X X X X X UP3-1 X UP2-1 1 0 0 X UPSL2 UPSL1 UP3 UP2 UP1 UP0 X X UP1-1 X X UP0-1 Write UPIO configuration bits. See Tables 19 and 22. Read UPIO configuration bits.
DIN
1
1
1
DIN
1
1
1
DOUTRB
X
X
X
SETTLING-TIME-MODE BITS 0 0 X X X X X X X X 1 1 1 X X X X 1 1 0 X X X X X X X X X X X X X SPDB X SPDB SPDA X SPDA Write DACA and DACB settling-time mode bits. Read DACA and DACB settling-time mode bits.
DIN
1
1
1
DIN
1
1
1
DOUTRB
X
X
X
CPOL AND CPHA CONTROL BITS 1 1 X X X X X X 0 0 0 1 X 0 0 0 0 X X X X X X X X X X X X X X X X CPOL X CPOL CPHA X CPHA Write CPOL, CPHA control bits. See Table 15. Read CPOL, CPHA control bits.
DIN
1
1
1
DIN
1
1
1
DOUTRB
X
X
X
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs
MAX5290-MAX5295
______________________________________________________________________________________
X = Don't care.
21
MAX5290-MAX5295
DATA BITS D1 D9 1 X X X X X X X X X D8 D7 D6 D5 D4 D3 D2 D1 D0 0 FUNCTION
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs
22
C0 D1 1 0 X X X X X X X RTP2 LF2 LR2 RTP1 LF1 LR1 Read UPIO_ inputs. (Valid only when UPIO1 or UPIO2 is configured as a general-purpose input.) See GPI, GPOL, GPOH section. Command is ignored. Command is ignored. Command is ignored. Command is ignored. 16-bit no-op command. All DACs are unaffected. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 X X X X X X X X 1 1 0 X X X X X X X X X 1 0 1 X X X X X X X X X 1 0 0 X X X X X X X X X
DATA BITS D24 D23 X 1 1 1 1 1 1 1 1 1 1 1 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 1 D11 1 D10 1 D9 1 D8 1 D7 X D6 D5 D4 D3 X X X X D2 X D1 X D0 X FUNCTION 1 0 X X X D23 D22 D21 D20 D19 D18 D17 D16 D15/ D14/ X X 1 D16 1 D15/ D14/ X X D13/ X 1 D13/ X D12/ X 1 D12/ X D11 D10 D9 D8 D7 1 X X X D23 D22 D21 D20 D19 D18 D17 1 X 1 1 1 1 1 1 1 1 1 D11 1 D10 1 D9 1 D8 X D7 Read input register A and DAC D3/ D2/ D1/ D0/ register A D6 D5 D4 X X X X (all 24 bits).** X X X X X X X Read input register B and DAC D3/ D2/ D1/ D0/ register B D6 D5 D4 X X X X (all 24 bits).**
Table 2b. Advanced-Feature Programming Commands (continued)
DATA
CONTROL BITS
C3
C2
C1
UPIO_ AS GPI (GENERAL-PURPOSE INPUT)
DIN
1
1
1
DOUTRB
X
X
X
OTHER COMMANDS
DIN
1
1
1
DIN
1
1
1
DIN
1
1
1
DIN
1
1
1
DIN
1
1
1
X = Don't care.
Table 2c. 24-Bit Read Commands
DATA
CONTROL BITS
C3
C2
C1
C0
D27 D26 D25
READ INPUT AND DAC REGISTERS A AND B
DIN
1
1
1
1
0
DOUTRB
X
X
X
X
X
DIN
1
1
1
1
0
______________________________________________________________________________________
DOUTRB
X
X
X
X
X
X = Don't care.
**D23-D12 represent the 12-bit data from the corresponding DAC register. D11-D0 represent the 12-bit data from the corresponding input register. For the MAX5292/MAX5293, bits D13, D12, D1, and D0 are don't-care bits. For the MAX5294/MAX5295, bits D15-D12 and D3-D0 are don't-care bits. During readback, all ones (code FF) must be clocked into DIN for all 24 bits. No command may be issued before all 24 bits have been clocked out. CS must be kept low while all 24 bits are clocked out.
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs
Default register values at power-up correspond to the state of PU, e.g. input and DAC registers are set to 800hex if PU is floating, FFFhex if PU = DV DD, and 000hex if PU= DGND. DAC Programming Examples: To load input register A from the shift register, leaving DAC register A unchanged (DAC output unchanged), use the command in Table 3. The MAX5290-MAX5295 can load DAC register A from the shift register, leaving input register A unchanged, by using the command in Table 4. To load input register A and DAC register A simultaneously from the shift register, use the command in Table 5. For the 10-bit and 8-bit versions, set sub-bits = 0 for best performance.
Advanced Feature Programming Commands
Refer to the Programmer's Handbook for details. Select Bits (MA, MB) The select bits allow synchronous updating of any combination of channels. The select bits command the loading of the DAC register from the input register of each channel. Set the select bit M_ = 1 to load the DAC register "_" with data from the input register "_", where "_" is replaced with A or B depending on the selected channel. Setting the select bit to M_ = 0 results in no action for that channel (Table 6).
MAX5290-MAX5295
Table 3. Load Input Register A from Shift Register
DATA DIN CONTROL BITS 0 0 0 0 D11 D10 D9 D8 D7 DATA BITS D6 D5 D4 D3/0 D2/0 D1/0 D0/0
Table 4. Load DAC Register A from Shift Register
DATA DIN CONTROL BITS 0 0 0 1 D11 D10 D9 D8 D7 DATA BITS D6 D5 D4 D3/0 D2/0 D1/0 D0/0
Table 5. Load Input Register A and DAC Register A from Shift Register
DATA DIN CONTROL BITS 0 0 1 0 D11 D10 D9 D8 D7 DATA BITS D6 D5 D4 D3/0 D2/0 D1/0 D0/0
Table 6. Select Command
DATA DIN CONTROL BITS 1 1 1 0 0 0 X X X DATA BITS X X X X X MB MA
X = Don't care.
Table 7. Select Bits Programming Example
DATA DIN CONTROL BITS 1 1 1 0 0 0 X X X DATA BITS X X X X X 1 0
X = Don't care.
______________________________________________________________________________________
23
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs MAX5290-MAX5295
Select Bits Programming Example: To load DAC register B from input register B while keeping channel A unchanged, set MB = 1 and MA = 0, as in the command in Table 7. Shutdown-Mode Bits (PDA0, PDA1, PDB0, PDB1) Use the shutdown-mode bits to shut down each DAC independently. Set PD_0 and PD_1 according to Table 8 to select the shutdown mode for DAC_, where "_" is replaced with A or B depending on the selected channel. The three possible states for unity-gain versions are 1) normal operation, 2) shutdown with 1k output impedance, and 3) shutdown with 100k output impedance. The three possible states for force-sense versions are 1) normal operation, 2) shutdown with 1k output impedance, and 3) shutdown with high-impedance output. Table 9 shows the command for writing to the shutdown mode bits. Shutdown-Mode Bits Write Example: To put a unity-gain version's DACA into shutdown mode with internal 1k termination to ground and DACB into the shutdown mode with the internal 100k termination to ground, use the command in Table 10 (applicable to unity-gain output only). To read back the shutdown-mode bits, use the command in Table 11.
Table 8. Shutdown-Mode Bits
PD_1 0 PD_0 0 DESCRIPTIONS Shutdown with 1k termination to ground on DAC_ output. Shutdown with 100k termination to ground on DAC_ output for unity-gain versions. Shutdown with high-impedance output for force-sense versions. Ignored. DAC_ is powered up in its normal operating mode.
0
1
1 1
0 1
Table 9. Shutdown-Mode Write Command
DATA DIN CONTROL BITS 1 1 1 0 0 1 0 X X DATA BITS X X X PDB1 PDB0 PDA1 PDA0
X = Don't care.
Table 10. Shutdown-Mode Bits Write Example
DATA DIN CONTROL BITS 1 1 1 0 0 1 0 X X DATA BITS X X X 0 1 0 0
X = Don't care.
Table 11. Shutdown-Mode Read Command
DATA DIN DOUTRB 1 X CONTROL BITS 1 X 1 X 0 X 0 X 1 X 1 X X X X X DATA BITS X X X X X X X X X X PDB1 PDB0 PDA1 PDA0
X = Don't care.
Table 12. Settling-Time-Mode Write Command
DATA DIN CONTROL BITS 1 1 1 0 1 1 0 X X DATA BITS X X X X X SPDB SPDA
X = Don't care.
24
______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs
Settling-Time-Mode Bits (SPDA, SPDB) The settling-time-mode bits select the settling time (FAST mode or SLOW mode) of the MAX5290- MAX5295. Set SPD_ = 1 to select FAST mode or set SPD_ = 0 to select SLOW mode, where "_" is replaced by A or B, depending on the selected channel (see Table 12). FAST mode provides a 3s maximum settling time and SLOW mode provides a 10s maximum settling time. Default settling-time mode bits are [0, 0] (SLOW mode for both DACs). Settling-Time-Mode Write Example: To configure DACA into FAST mode and DACB into SLOW mode, use the command in Table 13. To read back the settling-time-mode bits, use the command in Table 14. CPOL and CPHA Control Bits The CPOL and CPHA control bits of the MAX5290-MAX5295 are defined the same as the CPOL and CPHA bits in the SPI standard. Set the CPOL = 0 and CPHA = 0 or set CPOL = 1 and CPHA = 1 for MICROWIRE and SPI applications requiring the clocking of data in on the rising edge of SCLK. Set the CPOL = 0
MAX5290-MAX5295
Table 13. Settling-Time-Mode Write Example
DATA DIN CONTROL BITS 1 1 1 0 1 1 0 X X DATA BITS X X X X X 0 1
X = Don't care.
Table 14. Settling-Time-Mode Read Command
DATA DIN DOUTRB 1 X CONTROL BITS 1 X 1 X 0 X 1 X 1 X 1 X X X X X DATA BITS X X X X X X X X X X X SPDB X SPDA
X = Don't care.
Table 15. CPOL and CPHA Bits
CPOL 0 0 1 1 CPHA 0 1 0 1 DESCRIPTION Default values at power-up when DSP is connected to DVDD. Data is clocked in on the rising edge of SCLK. Default values at power-up when DSP is connected to DGND. Data is clocked in on the falling edge of SCLK. Data is clocked in on the falling edge of SCLK. Data is clocked in on the rising edge of SCLK.
Table 16. CPOL and CPHA Write Command
DATA DIN CONTROL BITS 1 1 1 1 0 0 0 0 X DATA BITS X X X X X CPOL CPHA
X = Don't care.
Table 17. CPOL and CPHA Read Command
DATA DIN DOUTRB CONTROL BITS 1 X 1 X 1 X 1 X 0 X 0 X 0 X 1 X X X DATA BITS X X X X X X X X X X X X CPOL CPHA
X = Don't care. ______________________________________________________________________________________ 25
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs MAX5290-MAX5295
and CPHA = 1 or set CPOL = 1 and CPHA = 0 for DSP and SPI applications requiring the clocking of data in on the falling edge of SCLK (refer to the Programmer's Handbook and see Table 15 for details). At power-up, if DSP = DVDD, the default value of CPHA is zero and if DSP = DGND, the default value of CPHA is one. The default value of CPOL is zero at power-up. To write to the CPOL and CPHA bits, use the command in Table 16. To read back the device's CPOL and CPHA bits, use the command in Table 17. UPIO Bits (UPSL1, UPSL2, UP0-UP3) The MAX5290-MAX5295 provide two user-programmable input/output (UPIO) ports: UPIO1 and UPIO2. These ports have 15 possible configurations, as shown in Table 22. UPIO1 and UPIO2 can be programmed independently or simultaneously by writing to the UPSL1, UPSL2, and UP0-UP3 bits (see Table 18). Table 19 shows how UPIO1 and UPIO2 are selected for configuration. The UP0-UP3 bits select the desired functions for UPIO1 and/or UPIO2 (see Table 22). Default states of UP10_ are high impedance. If using UP10_, connect 10k pullup resistors from each UPIO pin to DVDD. UPIO Programming Example: To set only UPIO1 as LDAC and leave UPIO2 unchanged, write the command in Table 20. The UPIO selection and configuration bits can be read back from the MAX5290-MAX5295 when UPIO1 or UPIO2 is configured as a DOUTRB output. Table 21 shows the read-back data format for the UPIO bits. Writing a 1110 101X XXXX XXXX initiates a read operation of the UPIO bits. The data is clocked out starting on the 9th clock cycle of the sequence. UP3-2 through UP0-2 provide the UP3-UP0 configuration bits for UPIO2 (see Table 22), and UP3-1 through UP0-1 provide the UP3-UP0 configuration bits for UPIO1.
Table 18. UPIO Write Command
DATA DIN CONTROL BITS 1 1 1 0 1 0 0 X DATA BITS UPSL2 UPSL1 UP3 UP2 UP1 UP0 X X
X = Don't care.
Table 19. UPIO Selection Bits (UPSL1 and UPSL2)
UPSL2 0 0 1 1 UPSL1 0 1 0 1 UPIO PORT SELECTED None selected UPIO1 selected UPIO2 selected Both UPIO1 and UPIO2 selected
Table 20. UPIO Programming Example
DATA DIN CONTROL BITS 1 1 1 0 1 0 0 X 0 DATA BITS 1 0 0 0 0 X X
X = Don't care.
Table 21. UPIO Read Command
DATA DIN DOUTRB 1 X CONTROL BITS 1 X 1 X 0 X 1 X 0 X 1 X X X X DATA BITS X X X X X X X UP3-2 UP2-2 UP1-2 UP0-2 UP3-1 UP2-1 UP1-1 UP0-1
X = Don't care. 26 ______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs
User-Programmable Input/Output (UPIO) Configuration
Table 22 lists the possible configurations for UPIO1 and UPIO2. UPIO1 and UPIO2 use the selected function when configured by the UP3-UP0 configuration bits. Drive LDAC low to asynchronously load the DAC registers from their corresponding input registers (DACs that are in shutdown remain shut down). The LDAC function does not require any activity on CS, SCLK, or DIN. If LDAC is brought low coincident with a rising edge of CS, (which executes a serial command modifying the value of either DAC input register), then LDAC must remain asserted for at least 120ns following the CS rising edge. This requirement applies only to serial commands that modify the value of the DAC input registers. See Figures 5 and 6 for timing details.
MAX5290-MAX5295
LDAC LDAC controls loading of the DAC registers. When LDAC is high, the DAC registers are latched, and any change in the input registers does not affect the contents of the DAC registers or the DAC outputs. When LDAC is low, the DAC registers are transparent, and the values stored in the input registers are fed directly to the DAC registers, and the DAC outputs are updated.
Table 22. UPIO Configuration Register Bits (UP3-UP0)
UPIO CONFIGURATION BITS UP3 0 0 0 0 0 0 0 UP2 0 0 0 0 1 1 1 UP1 0 0 1 1 0 0 1 UP0 0 1 0 1 0 1 0 FUNCTION LDAC SET MID CLR PDL Reserved SHDN1K DESCRIPTION Active-Low Load DAC Input. Drive low to asynchronously load all DAC registers with data from input registers. Active-Low Input. Drive low to set all input and DAC registers to full scale. Active-Low Input. Drive low to set all input and DAC registers to midscale. Active-Low Input. Drive low to set all input and DAC registers to zero scale. Active-Low Power-Down Lockout Input. Drive low to disable software shutdown. This mode is reserved. Do not use. Active-Low 1k Shutdown Input. Overrides PD_1 and PD_0 settings. Drive SHDN1K low to pull OUTA and OUTB to AGND with 1k.
0
1
1
1
Active-Low 100k Shutdown Input. Overrides PD_1 and PD_0 settings. For the MAX5290/MAX5292/MAX5294, drive SHDN100K low to pull OUTA and OUTB to SHDN100K AGND with 100k. For the MAX5291/MAX5293/MAX5295, drive SHDN100K low to leave OUTA and OUTB high impedance. DOUTRB DOUTDC0 DOUTDC1 GPI GPOL GPOH TOGG Data Read-Back Output Mode 0 Daisy-Chain Data Output. Data is clocked out on the falling edge of SCLK. Mode 1 Daisy-Chain Data Output. Data is clocked out on the rising edge of SCLK. General-Purpose Logic Input General-Purpose Logic-Low Output General-Purpose Logic-High Output Toggle Input. Toggles DAC outputs between data in input registers and data in DAC registers. Drive low to set all DAC outputs to values stored in input registers. Drive high to set all DAC outputs to values stored in DAC registers. FAST/SLOW Settling-Time Mode Input. Drive low to select FAST mode (3s) or drive high to select SLOW settling mode (10s). Overrides the SPDA and SPDB settings.
1 1 1 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 0 1
0 1 0 1 0 1 0
1
1
1
1
FAST
______________________________________________________________________________________
27
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs MAX5290-MAX5295
SET, MID, CLR The SET, MID, and CLR signals force the DAC outputs to full scale, midscale, or zero scale (Figure 5). These signals cannot be active at the same time. The active-low SET input forces the DAC outputs to full scale when SET is low. When SET is high, the DAC outputs follow the data in the DAC registers. The active-low MID input forces the DAC outputs to midscale when MID is low. When MID is high, the DAC outputs follow the data in the DAC registers. The active-low CLR input forces the DAC outputs to zero scale when CLR is low. When CLR is high, the DAC outputs follow the data in the DAC registers. If CLR, MID, or SET signals go low in the middle of a write command, reload the data to ensure accurate results.
Power-Down Lockout (PDL) The PDL active-low software-shutdown lockout input overrides (not overwrites), the PD_0 and PD_1 shutdown mode bits. PDL cannot be active at the same time as SHDN1K or SHDN100K (see the Shutdown Mode (SHDN1K, SHDN100K) section). If the PD_0 and PD_1 bits command the DAC to shut down prior to PDL going low, the DAC returns to shutdown mode immediately after PDL goes high, unless the PD_0 and PD_1 bits are changed in the meantime.
tLDL LDAC
TOGG
PDL tCMS CLR, MID, OR SET tS VOUT_ PDL AFFECTS DAC OUPTUTS (VOUT_) ONLY IF DACS WERE PREVIOUSLY SHUT DOWN. 0.5 LSB
Figure 5. Asynchronous Signal Timing
END OF CYCLE*
tGP
GPO_ LDAC tLDS
S Shutdown Mode (SHDN1K, SHDN100K) The SHDN1K and SHDN100K are active-low signals that override (not overwrite) the PD_1 and PD_0 bit settings. For the MAX5290/MAX5292/MAX5294, drive SHDN1K low to select shutdown mode with OUTA and OUTB internally terminated with 1k to ground, or drive SHDN100K low to select shutdown with an internal 100k termination. For the MAX5291/MAX5293/ MAX5295, drive SHDN1K low for shutdown with 1k output termination, or drive SHDN100K low for shutdown with high-impedance outputs.
Data Output (DOUTRB, DOUTDC0, DOUTDC1) UPIO1 and UPIO2 can be configured as serial data outputs, DOUTRB (data out for read back), DOUTDC0 (data out for daisy-chaining, mode 0), and DOUTDC1 (data out for daisy-chaining, mode 1). The differences between DOUTRB and DOUTDC0 (or DOUTDC1) are as follows:
*END-OF-CYCLE REPRESENTS THE RISING EDGE OF CS OR THE 16TH ACTIVE CLOCK EDGE, DEPENDING ON THE MODE OF OPERATION.
Figure 6. GPO_ and LDAC Signal Timing
*
The source of read-back data on DOUTRB is the DOUT register. Daisy-chain DOUTDC_ data comes directly from the shift register. * Read-back data on DOUTRB is only present after a DAC read command. Daisy-chain data is present on DOUTDC_ for any DAC write after the first 16 bits are written. * The DOUTRB idle state (CS = high) for read back is high impedance. Daisy-chain DOUTDC_ idles high when inactive to avoid floating the data input in the next device in the daisy-chain. See Figures 1 and 2 for timing details.
28
______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs
GPI, GPOL, GPOH UPIO1 and UPIO2 can each be configured as a general-purpose logic input (GPI), a general-purpose logiclow output (GPOL), or general-purpose logic-high output (GPOH). The GPI can detect interrupts from Ps or microcontrollers. It provides three functions: 1) Sample the signal at GPI at the time of the read (RTP1 and RTP2). 2) Detect whether or not a falling edge has occurred since the last read or reset (LF1 and LF2). 3) Detect whether or not a rising edge has occurred since the last read or reset (LR1 and LR2). RTP1, LF1, and LR1 represent the data read from UPIO1. RTP2, LF2, and LR2 represent the data read from UPIO2. To issue a read command for the UPIO configured as GPI, use the command in Table 23. Once the command is issued, RTP1 and RTP2 provide the real-time status (0 or 1) of the inputs at UPIO1 or UPIO2, respectively, at the time of the read. If LF2 or LF1 is one, then a falling edge has occurred on the UPIO1 or UPIO2 input since the last read or reset. If LR2 or LR1 is one, then a rising edge has occurred since the last read or reset. GPOL outputs a constant logic low, and GPOH outputs a constant logic high (see Figure 6). TOGG Use the TOGG input to toggle a DAC output between the values in the input register and DAC register. A delay of greater than 100ns from the end of the previous write command is required before the TOGG signal can be correctly switched between the new value and the previously stored value. When TOGG = 0, the output follows the information in the input registers. When TOGG = 1, the output follows the information in the DAC register (Figure 5).
MAX5290-MAX5295
FAST The MAX5290-MAX5295 have two settling-time-mode options: FAST (3s max at 12 bits) and SLOW (6s max at 12 bits). To select the FAST mode, drive FAST low, and to select SLOW mode, drive FAST high. This overrides (not overwrites) the SPDA and SPDB bit settings.
Table 23. GPI Read Command
DATA DIN DOUTRB CONTROL BITS 1 X 1 X 1 X 1 X 0 X 0 X 1 X X X X X DATA BITS X X X RTP2 X LF2 X LR2 X RTP1 X LF1 X LR1
X = Don't care.
Table 24. Unipolar Code Table (Gain = +1)
DAC CONTENTS MSB 1111 1000 1000 0111 0000 0000 1111 0000 0000 1111 0000 0000 LSB 1111 0001 0000 1111 0001 0000 ANALOG OUTPUT
REF DAC_ OUT_ VOUT_ = VREF x CODE / 4096 CODE IS THE DAC_ INPUT CODE (0 TO 4095 DECIMAL).
+VREF (4095 / 4096) +VREF (2049 / 4096) +VREF (2048 / 4096) = VREF / 2 +VREF (2047 / 4096) +VREF (1 / 4096) 0
MAX5290
Figure 7. Unipolar Output Circuit
______________________________________________________________________________________
29
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs MAX5290-MAX5295
Applications Information
Unipolar Output
Figure 7 shows the unity gain of the MAX5290 in a unipolar output configuration. Table 24 lists the unipolar output codes.
Configurable Output Gain
The MAX5291/MAX5293/MAX5295 have force-sense outputs, which provide a connection directly to the inverting terminal of the output op amp, yielding the most flexibility. The advantage of the force-sense output is that specific gains can be set externally for a given application. The gain error for the MAX5291/MAX5293/MAX5295 is specified in a unity-gain configuration (op-amp output and inverting terminals connected) and additional gain error results from external resistor tolerances. The force-sense DACs allow many useful circuits to be created with only a few simple external components. An example of a custom, fixed gain using the MAX5291's force-sense output is shown in Figure 9. In this example, the external reference is set to 1.25V, and the gain is set to +1.1V/V with external discrete resistors to provide an approximate 0 to 1.375V DAC output voltage range. VOUT_ = [(0.5 x VREF x CODE) / 4096] x [1 + (R2 / R1)] where CODE represents the numeric value of the DAC's binary input code (0 to 4095 decimal). In this example, if R2 = 12k and R1 = 10k, set the gain = 1.1V/V: VOUT_ = [(0.5 x 1.25V x CODE) / 4096] x 2.2
Bipolar Output
The MAX5290 outputs can be configured for bipolar operation, as shown in Figure 8. The output voltage is given by the following equation: VOUT_ = VREF x (CODE - 2048) / 2048 where CODE represents the numeric value of the DAC's binary input code (0 to 4095 decimal). Table 25 shows digital codes and the corresponding output voltage for the Figure 8 circuit.
Table 25. Bipolar Code Table (Gain = +1)
DAC CONTENTS MSB 1111 1000 1000 0111 0000 0000 1111 0000 0000 1111 0000 0000 LSB 1111 0001 0000 1111 0001 0000 ANALOG OUTPUT +VREF (2047 / 2048) +VREF (1 / 2048) 0 +VREF (1 / 2048) -VREF (2047 / 2048) -VREF (2048 / 2048) = -VREF
10k
10k V+ VOUT_
REF
DAC_ OUT_ R2 = 12k 0.1% 25ppm FB_
REF
DAC_ OUT_ V-
MAX5291
MAX5290
R1 = 10k 0.1% 25ppm
Figure 8. Bipolar Output Circuit
Figure 9. Configurable Output Gain
30
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Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs
Power-Supply and Layout Considerations
Bypass the analog and digital power supplies with a 10F capacitor in parallel with a 0.1F capacitor to analog ground (AGND) and digital ground (DGND) (see Figure 10). Minimize lead lengths to reduce lead inductance. If noise is an issue, use shielding and/or ferrite beads to increase isolation. Digital and AC transient signals coupling to AGND create noise at the output. Connect AGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane. Wire-wrapped boards and sockets are not recommended. For optimum system performance, use printed circuit (PC) boards with separate analog and digital ground planes. Connect the two ground planes together at the low-impedance powersupply source. Using separate power supplies for AVDD and DVDD improves noise immunity. Connect AGND and DGND at the low-impedance power-supply source (see Figure 11).
MAX5290-MAX5295
AVDD
DVDD
0.1F VREF REF 10F* 0.1F* CS SCLK DIN PU DSP UPIO1 UPIO2 AVDD
10F DVDD
0.1F
10F
ANALOG SUPPLY AVDD AGND
DIGITAL SUPPLY DVDD DGND
MAX5290-MAX5295
MAX5291/ MAX5293/ MAX5295 ONLY
OUTA FBA FBB
10F
10F
0.1F
OUTB
0.1F
AVDD
AGND** DGND**
AGND
DVDD
DGND
DVDD
DGND
MAX5290-MAX5295
*REMOVE BYPASS CAPACITORS ON REF FOR AC-REFERENCE INPUTS. **CONNECT ANALOG AND DIGITAL GROUND PLANES AT THE LOW-IMPEDANCE POWER-SUPPLY SOURCE.
DIGITAL CIRCUITRY
Figure 10. Bypassing Power Supplies and Reference
Figure 11. Separate Analog and Digital Power Supplies
______________________________________________________________________________________
31
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs MAX5290-MAX5295
Pin Configurations
TOP VIEW
UPIO1 1 DSP DIN 2 3 14 UPIO2 13 PU 12 OUTA UPIO2 1 UPIO1 2 DSP 3 DIN 4 CS 5 SCLK 6 DVDD 7 DGND 8 16 PU 15 OUTA 14 FBA
CS 4 SCLK 5 DVDD 6 DGND 7
MAX5290 MAX5292 MAX5294
11 REF 10 OUTB 9 8 AVDD AGND
MAX5291 MAX5293 MAX5295
13 REF 12 FBB 11 OUTB 10 AVDD 9 AGND
14 TSSOP
UPIO1 UPIO2 PU N.C.
16 TSSOP
UPIO1 UPIO2 PU OUTA
16
DSP DIN CS SCLK
15
14
13 12
OUTA N.C. REF OUTB DSP DIN CS SCLK
16 1 2 3 4 5
DVDD
15
14
13 12
FBA REF FBB OUTB
1 2 3 4 5
DVDD
MAX5290 MAX5292 MAX5294
6
DGND
11 10 9 8
AVDD
MAX5291 MAX5293 MAX5295
6
DGND
11 10 9 8
AVDD
7
AGND
7
AGND
(4mm x 4mm) THIN QFN
(4mm x 4mm) THIN QFN
Selector Guide
PART MAX5290AEUD MAX5290BEUD MAX5290AETE* MAX5290BETE MAX5291AEUE MAX5291BEUE MAX5291AETE* MAX5291BETE MAX5292EUD MAX5292ETE MAX5293EUE MAX5293ETE MAX5294EUD MAX5294ETE MAX5295EUE MAX5295ETE OUTPUT RESOLUTION BUFFER (BITS) CONFIGURATION Unity Gain Unity Gain Unity Gain Unity Gain Force Sense Force Sense Force Sense Force Sense Unity Gain Unity Gain Force Sense Force Sense Unity Gain Unity Gain Force Sense Force Sense 12 12 12 12 12 12 12 12 10 10 10 10 8 8 8 8 INL (LSBs MAX) 1 4 1 4 1 4 1 4 1 1 1 1 0.5 0.5 0.5 0.5
Chip Information
TRANSISTOR COUNT: 16,758 PROCESS: BiCMOS
*Future product--contact factory for availability. Specifications are preliminary. 32 ______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
PACKAGE OUTLINE, TSSOP 4.40mm BODY
MAX5290-MAX5295
21-0066
I
1 1
______________________________________________________________________________________
33
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs MAX5290-MAX5295
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
F
1 2
34
______________________________________________________________________________________
24L QFN THIN.EPS
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX5290-MAX5295
PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
F
2 2
Revision History
Pages changed at Rev 3: 1, 6-9, 33, 34, 35
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 35 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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